SEMICONDUCTOR MEMORY

PURPOSE: To perform perfect transfer of data by forbiding the moving operation of data in a register in a prescribed duration after receiving an external transfer signal. CONSTITUTION: Switches 56, 58 are connected in a first mode so that the outputs of tap latches 42, 46 are inputed in series to th...

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Bibliographische Detailangaben
Hauptverfasser: JIERII AARU BANAKEN, FUREDERITSUKU EI BARENTE, KAARU EMU GUTATSUGU, REIMONDO PINKUHAMU, DANIERU EFU ANDAASON
Format: Patent
Sprache:eng
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Zusammenfassung:PURPOSE: To perform perfect transfer of data by forbiding the moving operation of data in a register in a prescribed duration after receiving an external transfer signal. CONSTITUTION: Switches 56, 58 are connected in a first mode so that the outputs of tap latches 42, 46 are inputed in series to the related shift registers 34, 38, respectively. Similarly, when switches 60, 62 are closed, the outputs of tap latches 44, 48 are connected to shift registers 36, 40 in series. In a second mode, switches 56, 58 are composed so that tap outputs of registers 34, 38 are inputted in series to the registers 36, 40. At this time, the swiches 60, 62 are located on open positions and circulation of data in the registers 36, 40 is forbidden.