SMALL-REGION BIPOLAR TRANSISTOR

PURPOSE: To reduce latch up between adjoining NMOS and PMOS transistors by forming an emitter using a divided silicon deposition method. CONSTITUTION: A second polycrystalline silicon layer 126 is deposited on the entire surface of a processed wafer, for consolidation with a first layer 112. The second polycrystalline layer 126 forms a polysilicon composite layer 128 on a gate oxide 111 consisting of NMOS and PMOS transistors, a true poly- emitter, base interface district 125 of bipolar, and a collector 110. The polysilicon 128 is injected with such a high dosage of an N-type impurity as phosphorus (132). With polysilicon overlapped with the gate oxide 111, which is strongly doped and etched with a specified pattern, a gate conductor to respective NMOS and PMOS transistors is formed. Thereby, a lap between adjoining NMOS and PMOS transistors is reduced.