SEMICONDUCTOR MEMORY DEVICE

PURPOSE:To enable memory capacity to be increased and these to be laid out easily by extending and placing an address decoder for forming word line selection signal and a word line drive circuit in a parallel direction of each bit line. CONSTITUTION:A word driver 2 and a row address decoder 3 are ex...

Ausführliche Beschreibung

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Bibliographische Detailangaben
Hauptverfasser: MURANAKA MASAYA, SUZUKI YUKIE, MATSUURA NOBUMI
Format: Patent
Sprache:eng
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Beschreibung
Zusammenfassung:PURPOSE:To enable memory capacity to be increased and these to be laid out easily by extending and placing an address decoder for forming word line selection signal and a word line drive circuit in a parallel direction of each bit line. CONSTITUTION:A word driver 2 and a row address decoder 3 are extended and placed by directing them in a parallel direction of each complimentary bit lines DL0, DO0* (* indicates inversion or row enable) - DLn, DLn* and a unit circuit of the decoder 3 and the driver 2 can be placed matching pitch of a complimentary pitch line where the pitch is larger than that of word lines WL1 - WLm, thus enabling the driver 2 and the decoder 3 to be placed easily even if the wiring pitch is small accompanied by increase in memory capacity and miniaturization of circuit element.