MEMORY DEVICE AND DIGITAL SIGNAL PROCESSING UNIT

PURPOSE:To attain high speed access with simple constitution and to reduce power consumption by using a cyclic shift register so as to access directly a memory word line and deviating a word line accessed one by one line once for one sampling period. CONSTITUTION:Each output of cyclic shift registers 101-10n of an access circuit 3 is connected to word lines W1-Wn of an n-word RAM 1. A counter 4 of a coefficient ROM section 301 receives one sampling data for every n-count and outputs a carry signal CA when the count is finished for n-times. Upon the detection of the signal CA, a control circuit 5 outputs a bypass shift signal SHIFT 1, the registers 101-10n shift a signal to one preceding register via transistors(TRs) 111-11n and writes a sampling data inputted newly to an address of a word line of the RAM 1 represented by the output of the register to be shifted. Thus, the write is implemented only once for one sampling period and high speed access and reduction in power consumption are attained with simple constitution.