LOGIC GATE

PURPOSE:To allow the gate to meet the requirements of high speed operation, low power consumption and full swing of logical amplitude simultaneously by employing a bipolar transistor for only a power supply side, operating a Bi-CMOS only at leading so as to prevent increase in a delay time. CONSTITUTION:When a signal fed to an input terminal IN changes from a level '1' to a level '0', a PMOS transistor(TR) 11 is turned on and NMOS TRs 12, 13 are turned off. Thus, a current is supplied to a resistor 16 and a base of an NPN bipolar TR 14. In this case, a voltage difference is produced across the resistor 16 and the TR 14 is turned on because a base-emitter voltage of the TR 14 rises. As a result, the load capacitor is quickly charged by an emitter current of the TR 14 and a signal of level '1' is outputted to an output terminal OUT. In this case, since the base and the emitter of the TR 14 is connected through a resistive element, a level '1' is swung fully up to a power supply voltage VDD fed to the source.