TIME SWITCH MEMORY

PURPOSE:To simplify a circuit configuration by inputting write data from a transfer gate provided on the head of a memory cell train and executing successively write, outputting read-out data from each data line and executing arbitrarily read-out. CONSTITUTION:At the time of data write, as for a dat...

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1. Verfasser:	TAKENO MINORU
Format:	Patent
Sprache:	eng
Schlagworte:	ELECTRIC COMMUNICATION TECHNIQUE ELECTRICITY SELECTING
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creator	TAKENO MINORU
description	PURPOSE:To simplify a circuit configuration by inputting write data from a transfer gate provided on the head of a memory cell train and executing successively write, outputting read-out data from each data line and executing arbitrarily read-out. CONSTITUTION:At the time of data write, as for a data input applied through a write amplifier 14, clock signals which become alternately '1' are applied to transfer gates 211, 212, 213,... of a write side from clock lines 231, 232. As a result, memory cells 111, 112, 113,... are shifted successively. When data is stored in all memory cells, when an address for arbitrary read-out is applied to an address decoder 17, the decoder 17 decodes it, and sets the designated address line in address lines 191, l92, 193,... to '1'. In such a way, data is read out to a data line 5 from the memory cell in the designated sequence.
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CONSTITUTION:At the time of data write, as for a data input applied through a write amplifier 14, clock signals which become alternately '1' are applied to transfer gates 211, 212, 213,... of a write side from clock lines 231, 232. As a result, memory cells 111, 112, 113,... are shifted successively. When data is stored in all memory cells, when an address for arbitrary read-out is applied to an address decoder 17, the decoder 17 decodes it, and sets the designated address line in address lines 191, l92, 193,... to '1'. In such a way, data is read out to a data line 5 from the memory cell in the designated sequence.</description><language>eng</language><subject>ELECTRIC COMMUNICATION TECHNIQUE ; ELECTRICITY ; SELECTING</subject><creationdate>1992</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=19920529&DB=EPODOC&CC=JP&NR=H04157895A$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,776,881,25542,76516</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=19920529&DB=EPODOC&CC=JP&NR=H04157895A$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>TAKENO MINORU</creatorcontrib><title>TIME SWITCH MEMORY</title><description>PURPOSE:To simplify a circuit configuration by inputting write data from a transfer gate provided on the head of a memory cell train and executing successively write, outputting read-out data from each data line and executing arbitrarily read-out. CONSTITUTION:At the time of data write, as for a data input applied through a write amplifier 14, clock signals which become alternately '1' are applied to transfer gates 211, 212, 213,... of a write side from clock lines 231, 232. As a result, memory cells 111, 112, 113,... are shifted successively. When data is stored in all memory cells, when an address for arbitrary read-out is applied to an address decoder 17, the decoder 17 decodes it, and sets the designated address line in address lines 191, l92, 193,... to '1'. In such a way, data is read out to a data line 5 from the memory cell in the designated sequence.</description><subject>ELECTRIC COMMUNICATION TECHNIQUE</subject><subject>ELECTRICITY</subject><subject>SELECTING</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>1992</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZBAK8fR1VQgO9wxx9lDwdfX1D4rkYWBNS8wpTuWF0twMim6uQGnd1IL8-NTigsTk1LzUknivAA8DE0NTcwtLU0djYtQAAEhYHmM</recordid><startdate>19920529</startdate><enddate>19920529</enddate><creator>TAKENO MINORU</creator><scope>EVB</scope></search><sort><creationdate>19920529</creationdate><title>TIME SWITCH MEMORY</title><author>TAKENO MINORU</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_JPH04157895A3</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>1992</creationdate><topic>ELECTRIC COMMUNICATION TECHNIQUE</topic><topic>ELECTRICITY</topic><topic>SELECTING</topic><toplevel>online_resources</toplevel><creatorcontrib>TAKENO MINORU</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>TAKENO MINORU</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>TIME SWITCH MEMORY</title><date>1992-05-29</date><risdate>1992</risdate><abstract>PURPOSE:To simplify a circuit configuration by inputting write data from a transfer gate provided on the head of a memory cell train and executing successively write, outputting read-out data from each data line and executing arbitrarily read-out. CONSTITUTION:At the time of data write, as for a data input applied through a write amplifier 14, clock signals which become alternately '1' are applied to transfer gates 211, 212, 213,... of a write side from clock lines 231, 232. As a result, memory cells 111, 112, 113,... are shifted successively. When data is stored in all memory cells, when an address for arbitrary read-out is applied to an address decoder 17, the decoder 17 decodes it, and sets the designated address line in address lines 191, l92, 193,... to '1'. In such a way, data is read out to a data line 5 from the memory cell in the designated sequence.</abstract><oa>free_for_read</oa></addata></record>
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title	TIME SWITCH MEMORY
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