CLOCK SIGNAL SKEW CIRCUIT

PURPOSE:To continue a stable operation with the clock signal of a low frequency even if PLL circuits are deviated from a lock state by detecting the unlock of the corresponding PLL circuit and selecting the output of a clock signal oscillator for standby. CONSTITUTION:The outputs of unlock detection circuits 13 and 23 in first and second integrated circuits 1 and 2 are connected to an OR circuit 31. When either unlock detection circuit outputs an alarm signal, the OR circuit outputs the alarm signal. A selector circuit 14 selects and outputs either the output of the PLL phase Looked Loop)circuit 12 being two inputs and the output of the clock oscillator for standby 21 by the output of the OR circuit 31. In such a case, the clock signal being the output of the PLL circuit 12 is usually selected when the alarm signal is not outputted to the output of the OR circuit 31. Thus, a clock signal skew circuit in which the logical circuit of a poststage can be maintained to normally operate even if there is the unlock of the PLL circuits 12 and 22 can be obtained.