MULTIPROCESSOR SYSTEM

PURPOSE:To prevent the dead lock due to access contention by setting an internal bus to the high impedance state to validate the access request from the system bus side in the case of contention between detection signals of two access request detecting means. CONSTITUTION:If access contention occurs in a bus interface if1' of a processor card C1', a contention monitor circuit detects this contention to output a contention detection signal. A control circuit for contention takes this signal as the input and sends a turning-off signal. Then, an internal bus b1 goes to the high impedance state. Next, the control circuit for contention outputs a contention confirmation signal indicating that the bus b1 goes to the high impedance state, and the contention monitor circuit receives this signal to output a start signal to a second bus interface. In this state, a processor card C2' acquires the bus right of the bus b1 of the card C1' through the bus interface and can access a RAM m1 by the address and data on a system bus SB which the card C2' outputs.