NONVOLATILE SEMICONDUCTOR MEMORY
PURPOSE:To simultaneously read from 1/2 memory cells, to merely transfer the read data to an output buffer and to read at a high speed by forming a pair of bit lines, dividing the bit line pair into two, and providing a sense amplifier at the center. CONSTITUTION:If a memory transistor 2M1 is read,...
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creator | HAYASHIGOE MASANORI |
description | PURPOSE:To simultaneously read from 1/2 memory cells, to merely transfer the read data to an output buffer and to read at a high speed by forming a pair of bit lines, dividing the bit line pair into two, and providing a sense amplifier at the center. CONSTITUTION:If a memory transistor 2M1 is read, a source line selecting signal SL becomes 'H', and the sources of memory transistors 2M1 to M4 are grounded. Precharge PRE and bit line selecting signals BLT11, BLT12, BLT22 become 'H', a bit line 4SL11 is precharged by a transistor 1Q14, and bit lines 4BL12, LB22 are precharged by a transistor 1Q15. The precharge capacities of the transistor 1A14, Q15 are equivalent, and the capacitance of a sense node 9SN1 becomes half of the capacitance of a sense node 9SN2. Accordingly, the sense nodes 9SN1, SN2 are precharged in an unbalance. That is, the potential of the node 9SN1 is higher than that of the node 9SH2. |
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CONSTITUTION:If a memory transistor 2M1 is read, a source line selecting signal SL becomes 'H', and the sources of memory transistors 2M1 to M4 are grounded. Precharge PRE and bit line selecting signals BLT11, BLT12, BLT22 become 'H', a bit line 4SL11 is precharged by a transistor 1Q14, and bit lines 4BL12, LB22 are precharged by a transistor 1Q15. The precharge capacities of the transistor 1A14, Q15 are equivalent, and the capacitance of a sense node 9SN1 becomes half of the capacitance of a sense node 9SN2. Accordingly, the sense nodes 9SN1, SN2 are precharged in an unbalance. That is, the potential of the node 9SN1 is higher than that of the node 9SH2.</description><language>eng</language><subject>BASIC ELECTRIC ELEMENTS ; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ; ELECTRICITY ; INFORMATION STORAGE ; PHYSICS ; SEMICONDUCTOR DEVICES ; STATIC STORES</subject><creationdate>1992</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=19920428&DB=EPODOC&CC=JP&NR=H04127478A$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,780,885,25563,76318</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=19920428&DB=EPODOC&CC=JP&NR=H04127478A$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>HAYASHIGOE MASANORI</creatorcontrib><title>NONVOLATILE SEMICONDUCTOR MEMORY</title><description>PURPOSE:To simultaneously read from 1/2 memory cells, to merely transfer the read data to an output buffer and to read at a high speed by forming a pair of bit lines, dividing the bit line pair into two, and providing a sense amplifier at the center. CONSTITUTION:If a memory transistor 2M1 is read, a source line selecting signal SL becomes 'H', and the sources of memory transistors 2M1 to M4 are grounded. Precharge PRE and bit line selecting signals BLT11, BLT12, BLT22 become 'H', a bit line 4SL11 is precharged by a transistor 1Q14, and bit lines 4BL12, LB22 are precharged by a transistor 1Q15. The precharge capacities of the transistor 1A14, Q15 are equivalent, and the capacitance of a sense node 9SN1 becomes half of the capacitance of a sense node 9SN2. Accordingly, the sense nodes 9SN1, SN2 are precharged in an unbalance. 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CONSTITUTION:If a memory transistor 2M1 is read, a source line selecting signal SL becomes 'H', and the sources of memory transistors 2M1 to M4 are grounded. Precharge PRE and bit line selecting signals BLT11, BLT12, BLT22 become 'H', a bit line 4SL11 is precharged by a transistor 1Q14, and bit lines 4BL12, LB22 are precharged by a transistor 1Q15. The precharge capacities of the transistor 1A14, Q15 are equivalent, and the capacitance of a sense node 9SN1 becomes half of the capacitance of a sense node 9SN2. Accordingly, the sense nodes 9SN1, SN2 are precharged in an unbalance. That is, the potential of the node 9SN1 is higher than that of the node 9SH2.</abstract><oa>free_for_read</oa></addata></record> |
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subjects | BASIC ELECTRIC ELEMENTS ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRICITY INFORMATION STORAGE PHYSICS SEMICONDUCTOR DEVICES STATIC STORES |
title | NONVOLATILE SEMICONDUCTOR MEMORY |
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