NONVOLATILE SEMICONDUCTOR MEMORY

PURPOSE:To simultaneously read from 1/2 memory cells, to merely transfer the read data to an output buffer and to read at a high speed by forming a pair of bit lines, dividing the bit line pair into two, and providing a sense amplifier at the center. CONSTITUTION:If a memory transistor 2M1 is read,...

Ausführliche Beschreibung

Gespeichert in:
Bibliographische Detailangaben
1. Verfasser: HAYASHIGOE MASANORI
Format: Patent
Sprache:eng
Schlagworte:
Online-Zugang:Volltext bestellen
Tags: Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
Beschreibung
Zusammenfassung:PURPOSE:To simultaneously read from 1/2 memory cells, to merely transfer the read data to an output buffer and to read at a high speed by forming a pair of bit lines, dividing the bit line pair into two, and providing a sense amplifier at the center. CONSTITUTION:If a memory transistor 2M1 is read, a source line selecting signal SL becomes 'H', and the sources of memory transistors 2M1 to M4 are grounded. Precharge PRE and bit line selecting signals BLT11, BLT12, BLT22 become 'H', a bit line 4SL11 is precharged by a transistor 1Q14, and bit lines 4BL12, LB22 are precharged by a transistor 1Q15. The precharge capacities of the transistor 1A14, Q15 are equivalent, and the capacitance of a sense node 9SN1 becomes half of the capacitance of a sense node 9SN2. Accordingly, the sense nodes 9SN1, SN2 are precharged in an unbalance. That is, the potential of the node 9SN1 is higher than that of the node 9SH2.