COMMUNICATION SYSTEM BETWEEN PLURAL PROCESSORS

PURPOSE:To suppress the amount of hardware, to eliminate a waiting time and to obtain the high speed processing to improve efficiency by preparing address space for communication between processors on a standard bus and providing a bus cycle generation circuit and a bus monitor circuit on each proce...

Ausführliche Beschreibung

Bibliographische Detailangaben

Hauptverfasser:	KAMIYA TOSHIZANE, NISHIJIMA TOSHIYA, TAKAI JUNICHI, HIROYA SHIYUUICHI, TAJIRI YASUSHI
Format:	Patent
Sprache:	eng
Schlagworte:	CALCULATING COMPUTING COUNTING ELECTRIC DIGITAL DATA PROCESSING PHYSICS
Online-Zugang:	Volltext bestellen
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