COMMUNICATION SYSTEM BETWEEN PLURAL PROCESSORS

PURPOSE:To suppress the amount of hardware, to eliminate a waiting time and to obtain the high speed processing to improve efficiency by preparing address space for communication between processors on a standard bus and providing a bus cycle generation circuit and a bus monitor circuit on each processor board. CONSTITUTION:The address space for communication between processors 1 to 3 is prepared on a standard bus 10, bus cycle generation circuits 11(a) to 13(a) and bus monitor circuits 11(b) to 13(b) are provided on each processor board 11 to 13, an internal ready is generated on the side of a transmitting processor at the time of write-in to the prescribed address of a standard bus 10 and an interrupt is executed for a receiving processor by the bus monitor circuits 11(b) to 13(b). At this time, a global memory and a 2 port memory are not required on the standard bus and the number of lines for interrupt request signals is small. Thus, the amount of hardware is suppressed, the waiting time is eliminated, the high speed of the processing is attained and the processing efficiency is improved.