FORMING METHOD OF VIA HOLE

PURPOSE:To form a via hole by using an electron-beam exposure technique by bonding the top face of a semiconductor substrate, in which an alignment mark is formed on the fixed substrate, with adhesives, etching the substrate from the underside of the substrate and exposing the mark. CONSTITUTION:Alignment marks 2 composed of Au and a pad electrode 7 are formed on the top face of a semi-insulating GaAs (a semiconductor substrate) 1 in thickness of approximately 100mum, and the top face of the substrate 1 is bonded with a glass substrate (a fixed substrate) 3 with a resin (adhesives) 4. The substrate 1 is etched from the undersides of the substrate 1 in regions including sections, to which the marks 2 are formed, the marks 2 bonded with the resin 4 are exposed, resists 5 for electron beams are shaped onto the substrate 1, the resists 5 are irradiated with electron beams based on the marks 2, and the resists 5 are developed. The substrate 1 is etched while using the resists 5 as masks, a via hole 6 is formed, the resists 5 are removed while the resin 4 is melted, and the substrate 1 is taken off from the substrate 3. Accordingly, the via hole can be formed by using an electron-beam exposure technique.