SEMICONDUCTOR MEMORY DEVICE AND MANUFACTURE THEREOF

PURPOSE:To reduce power consumption and further increase the degree of integration by using a low voltage parasitic MOS transistor where its load device is locally formed in a device isolation region in terms of 6 device SRAM memory cells. CONSTITUTION:At first on a P type Si substrate 41 is formed a device isolation oxide film 42, say, 5000Angstrom based on the application of a known selection oxidation technology. Then, a resist pattern 43 having an opening section is prepared where the opening section is arranged to be in a region which forms a parasitic MOS transistor of low threshold voltage. Furthermore, the oxide film is etched so that the remaining film may be 2000Angstrom , for example. N type impurities are ion-implanted in a thin oxide film region. For example, when P is implanted by 2000keV, 7X10 ions/cm, the threshold voltage will be about 0V. The gate oxide film, gate electrode, source/drain diffusion layers will be formed based on the known technology.