CACHE INOPERATIVE ADDRESS RANDOM ACCESS MEMORY

PURPOSE: To improve the flexibility of a computer system by providing a cache controller having a cache operation incapable address input and a cache operation incapable address programmable array logic or the like. CONSTITUTION: An output signal PALNCA* from a cache operation incapable address(NCA) programmable array logic(PAL) 12 is connected through a register 40 with an NCA* input of a cache controller C. Also, a memory writing processing used for reading or writing in an NCA RAM 14 is executed in a local bus mode decided by the NCA PAL 12, and the other memory existing except a local bus is not affected by the writing processing. Then, the signal PALNCA* is inputted to the controller C, so that additional flexibility can be obtained for the user and designer of a system, and the input of the signal NCA* to the controller C can be prevented, and interruption between signals generated by the PAL 12 and the RAM 14 can be prevented.