SCRAMBLER DESCRAMBLER CIRCUIT
PURPOSE:To allow the circuit to cope with high speed communication by obtaining exclusive OR between each bit of an input data and each bit of a scramble descramble data read from a storage means. CONSTITUTION:In the case of applying scramble descramble processing, each bit of an input data is input...
Gespeichert in:
Hauptverfasser: | , |
---|---|
Format: | Patent |
Sprache: | eng |
Schlagworte: | |
Online-Zugang: | Volltext bestellen |
Tags: |
Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
|
Zusammenfassung: | PURPOSE:To allow the circuit to cope with high speed communication by obtaining exclusive OR between each bit of an input data and each bit of a scramble descramble data read from a storage means. CONSTITUTION:In the case of applying scramble descramble processing, each bit of an input data is inputted to each one input terminal of plural exclusive OR circuits 131 and each bit of a scramble descramble data read from a storage means 111 is inputted to each other input terminal. Then each exclusive OR circuit 131 obtains exclusive OR of two inputs to obtain an output data, that is, a data resulting from applying scramble descrambling processing to the input data. Thus, the circuit can sufficiently cope with fast communication speed. |
---|