SCRAMBLER DESCRAMBLER CIRCUIT

PURPOSE:To allow the circuit to cope with high speed communication by obtaining exclusive OR between each bit of an input data and each bit of a scramble descramble data read from a storage means. CONSTITUTION:In the case of applying scramble descramble processing, each bit of an input data is input...

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Hauptverfasser: EGUCHI KATSUHIRO, KONO KENJI
Format: Patent
Sprache:eng
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Beschreibung
Zusammenfassung:PURPOSE:To allow the circuit to cope with high speed communication by obtaining exclusive OR between each bit of an input data and each bit of a scramble descramble data read from a storage means. CONSTITUTION:In the case of applying scramble descramble processing, each bit of an input data is inputted to each one input terminal of plural exclusive OR circuits 131 and each bit of a scramble descramble data read from a storage means 111 is inputted to each other input terminal. Then each exclusive OR circuit 131 obtains exclusive OR of two inputs to obtain an output data, that is, a data resulting from applying scramble descrambling processing to the input data. Thus, the circuit can sufficiently cope with fast communication speed.