HIGHER HARMONIC REDUCING FILTER

PURPOSE:To suppress PWM higher harmonics by inserting a circuit comprising an inductance, a capacitor and a resistor, connected in parallel, between a carrier frequency locked higher harmonic(PWM) inverter and a load and then resonating the circuit with frequency approximately two times of the carri...

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1. Verfasser: TAKAKADO YUZO
Format: Patent
Sprache:eng
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Beschreibung
Zusammenfassung:PURPOSE:To suppress PWM higher harmonics by inserting a circuit comprising an inductance, a capacitor and a resistor, connected in parallel, between a carrier frequency locked higher harmonic(PWM) inverter and a load and then resonating the circuit with frequency approximately two times of the carrier frequency. CONSTITUTION:A higher harmonic reducing filter 3 is a parallel circuit of an inductance 4, capacitor 5 and resistor 6, and the filter 3 is inserted between a PWM inverter 1 and each phase of a load 2. PWM higher harmonic composed of 2fc component is sufficiently suppressed with no influence on the basic wave when parallel resonance with frequency 2fc is induced by setting the inductance L of the inductance 4 and the capacitance C of the capacitor 5 are set such that 2fc=1/2 LC. By such arrangement, higher harmonic can be suppressed in a frequency region sufficiently higher than the basic frequency.