SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE

PURPOSE:To allow the potential of an operation mode setting terminal to change after the operation mode is set by providing a latch circuit latching an operating mode setting signal to a post-stage of a circuit. CONSTITUTION:When a CNVss terminal 1 at '0'V, the output of an inverter gate 2 reaches 5V (H level) and when a CNTL signal 8 is at an H level, the signal passes through inverter gates 12, 14 and an operating mode setting signal M116 goes to an H. Moreover, the input of the inverter gate 5 goes to '0'V (L level) and similarly an operating mode setting signal M017 goes to an H. Then the operating mode setting signal is reset when the CNTL signal is at an L and the CNTLB is at an H level, then the signal is latched by the inverter gates 12, 14 and the transmission gate 10, the level is kept to the operating mode setting signal and even when the level of the CNVss terminal 1 is changed, the operating mode is unchanged.