RECEPTION STATE DETECTION SYNCHRONIZING TYPE SERIAL COMMUNICATION SYSTEM

PURPOSE:To allow a sender side to detect whether or not data processing at the receiver side is normally implemented by sending back an inverted data when the data processing is not normally implemented. CONSTITUTION:A CPU generates a data read 19, reads a parallel data 12 via a data bus 20 and an i...

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1. Verfasser: TAKATANI KAZUHIKO
Format: Patent
Sprache:eng
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Zusammenfassung:PURPOSE:To allow a sender side to detect whether or not data processing at the receiver side is normally implemented by sending back an inverted data when the data processing is not normally implemented. CONSTITUTION:A CPU generates a data read 19, reads a parallel data 12 via a data bus 20 and an inverted control signal 18 being an output of a data read detection circuit 17 does not invert an inverting circuit 21. If the CPU is busy or the like and no data read signal 19 is generated, no parallel data 12 is read and an inverted control signal 16 being an output of the data read detection circuit 17 inverts the inverting circuit 21. Thus, one signal entering the comparator passes through the inverting circuit 21. Then whether or not the receiver side implements the data processing normally is detected by a processing output 3 at a sender side.