ADDRESS MODIFIABLE MEMORY ARRAY

PURPOSE:To read out data within the same time required as usual data read-out even if an address is modified by executing the modification of the address and the drive of a memory array in parallel. CONSTITUTION:When the address is fixed at timing A, the high order bit of the address and the displac...

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1. Verfasser: MIZUGAKI SHIGEO
Format: Patent
Sprache:eng
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Zusammenfassung:PURPOSE:To read out data within the same time required as usual data read-out even if an address is modified by executing the modification of the address and the drive of a memory array in parallel. CONSTITUTION:When the address is fixed at timing A, the high order bit of the address and the displacement are summed by an addition circuit 3. The time required for this addition is a period A. On the other hand, since a Y- decoder 5 starts to operate immediately after the address is fixed, the data of a word line 6 is fixed after the delay of the period B from the timing A, and further, the data of a bit line is fixed after the delay of the period C. Read- out data is fixed at the timing B after the delay time (period D) required for selecting the data by an X-decoder 7. As mentioned above, the time from the timing A to the timing B is the time required (access time) in the case where the data is read out after the address is modified, but this required time is the period B + the period C + the period D, that is, usual access time.