BUS CONTROL CIRCUIT FOR DMA TRANSFER

PURPOSE:To effectively use a CPU also during the period of DMA transfer to execute the processing of a task generated during the DMA transfer by disconnecting the CPU from DMA transfer requiring much time for transfer between an external bus and a buffer memory during the DMA transfer. CONSTITUTION:In a bus control circuit for DMA transfer, buffers 15a to 15c for disconnecting the CPU 1 from buses 11, 12 and a control line 13 at the time of DMA transfer between the external bus 5 and the buffer memory 14 and connecting the CPU 1 to the buses 11, 12 and the control line 13 after the DMA transfer is connected between the buffer memory 14 and a CPU memory 2. Consequently, the CPU 1 is driven at the time of the DMA transfer, the generated task is processed and rapid data transfer is attained.