METHOD OF TESTING ELECTRONIC CIRCUIT CONDITION

PURPOSE:To improve a test accuracy by setting the output of an electronic circuit component to be tested to a high impedance condition by a test mode signal in the electronic circuit component connected to the input side of the electronic circuit component to be tested. CONSTITUTION:Probes 60a-63a a...

Ausführliche Beschreibung

Gespeichert in:
Bibliographische Detailangaben
Hauptverfasser: SUGIO AKIMASA, MANBA HIROSHI, NAKAI JUNJI, TAKAHASHI TSUTOMU
Format: Patent
Sprache:eng
Schlagworte:
Online-Zugang:Volltext bestellen
Tags: Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
container_end_page
container_issue
container_start_page
container_title
container_volume
creator SUGIO AKIMASA
MANBA HIROSHI
NAKAI JUNJI
TAKAHASHI TSUTOMU
description PURPOSE:To improve a test accuracy by setting the output of an electronic circuit component to be tested to a high impedance condition by a test mode signal in the electronic circuit component connected to the input side of the electronic circuit component to be tested. CONSTITUTION:Probes 60a-63a are brought into contact with test pads 60b-63b, respectively. Then, a test mode signal S1 is inputted from a tester 64 to a tri-state buffer 53c via the probe 60a to set the output side lead 53b of an IC chip 53 to a high impedance condition. At the same time, a test drive signal S3 is inputted to the tri-state buffer 56c from the tester 64 to activate the try state buffer 56c. Thus, the effect of the IC chip 53 is removed over a range from a wiring pattern 57 to the IC chip 57.
format Patent
fullrecord <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_JPH03261882A</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>JPH03261882A</sourcerecordid><originalsourceid>FETCH-epo_espacenet_JPH03261882A3</originalsourceid><addsrcrecordid>eNrjZNDzdQ3x8HdR8HdTCHENDvH0c1dw9XF1Dgny9_N0VnD2DHIO9QxRcPb3c_EM8fT342FgTUvMKU7lhdLcDIpuriHOHrqpBfnxqcUFicmpeakl8V4BHgbGRmaGFhZGjsbEqAEA7i0mCQ</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>METHOD OF TESTING ELECTRONIC CIRCUIT CONDITION</title><source>esp@cenet</source><creator>SUGIO AKIMASA ; MANBA HIROSHI ; NAKAI JUNJI ; TAKAHASHI TSUTOMU</creator><creatorcontrib>SUGIO AKIMASA ; MANBA HIROSHI ; NAKAI JUNJI ; TAKAHASHI TSUTOMU</creatorcontrib><description>PURPOSE:To improve a test accuracy by setting the output of an electronic circuit component to be tested to a high impedance condition by a test mode signal in the electronic circuit component connected to the input side of the electronic circuit component to be tested. CONSTITUTION:Probes 60a-63a are brought into contact with test pads 60b-63b, respectively. Then, a test mode signal S1 is inputted from a tester 64 to a tri-state buffer 53c via the probe 60a to set the output side lead 53b of an IC chip 53 to a high impedance condition. At the same time, a test drive signal S3 is inputted to the tri-state buffer 56c from the tester 64 to activate the try state buffer 56c. Thus, the effect of the IC chip 53 is removed over a range from a wiring pattern 57 to the IC chip 57.</description><language>eng</language><subject>CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS ; ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR ; ELECTRICITY ; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS ; MEASURING ; MEASURING ELECTRIC VARIABLES ; MEASURING MAGNETIC VARIABLES ; PHYSICS ; PRINTED CIRCUITS ; TESTING</subject><creationdate>1991</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=19911121&amp;DB=EPODOC&amp;CC=JP&amp;NR=H03261882A$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,309,781,886,25566,76549</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=19911121&amp;DB=EPODOC&amp;CC=JP&amp;NR=H03261882A$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>SUGIO AKIMASA</creatorcontrib><creatorcontrib>MANBA HIROSHI</creatorcontrib><creatorcontrib>NAKAI JUNJI</creatorcontrib><creatorcontrib>TAKAHASHI TSUTOMU</creatorcontrib><title>METHOD OF TESTING ELECTRONIC CIRCUIT CONDITION</title><description>PURPOSE:To improve a test accuracy by setting the output of an electronic circuit component to be tested to a high impedance condition by a test mode signal in the electronic circuit component connected to the input side of the electronic circuit component to be tested. CONSTITUTION:Probes 60a-63a are brought into contact with test pads 60b-63b, respectively. Then, a test mode signal S1 is inputted from a tester 64 to a tri-state buffer 53c via the probe 60a to set the output side lead 53b of an IC chip 53 to a high impedance condition. At the same time, a test drive signal S3 is inputted to the tri-state buffer 56c from the tester 64 to activate the try state buffer 56c. Thus, the effect of the IC chip 53 is removed over a range from a wiring pattern 57 to the IC chip 57.</description><subject>CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS</subject><subject>ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRICITY</subject><subject>MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS</subject><subject>MEASURING</subject><subject>MEASURING ELECTRIC VARIABLES</subject><subject>MEASURING MAGNETIC VARIABLES</subject><subject>PHYSICS</subject><subject>PRINTED CIRCUITS</subject><subject>TESTING</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>1991</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZNDzdQ3x8HdR8HdTCHENDvH0c1dw9XF1Dgny9_N0VnD2DHIO9QxRcPb3c_EM8fT342FgTUvMKU7lhdLcDIpuriHOHrqpBfnxqcUFicmpeakl8V4BHgbGRmaGFhZGjsbEqAEA7i0mCQ</recordid><startdate>19911121</startdate><enddate>19911121</enddate><creator>SUGIO AKIMASA</creator><creator>MANBA HIROSHI</creator><creator>NAKAI JUNJI</creator><creator>TAKAHASHI TSUTOMU</creator><scope>EVB</scope></search><sort><creationdate>19911121</creationdate><title>METHOD OF TESTING ELECTRONIC CIRCUIT CONDITION</title><author>SUGIO AKIMASA ; MANBA HIROSHI ; NAKAI JUNJI ; TAKAHASHI TSUTOMU</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_JPH03261882A3</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>1991</creationdate><topic>CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS</topic><topic>ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRICITY</topic><topic>MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS</topic><topic>MEASURING</topic><topic>MEASURING ELECTRIC VARIABLES</topic><topic>MEASURING MAGNETIC VARIABLES</topic><topic>PHYSICS</topic><topic>PRINTED CIRCUITS</topic><topic>TESTING</topic><toplevel>online_resources</toplevel><creatorcontrib>SUGIO AKIMASA</creatorcontrib><creatorcontrib>MANBA HIROSHI</creatorcontrib><creatorcontrib>NAKAI JUNJI</creatorcontrib><creatorcontrib>TAKAHASHI TSUTOMU</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>SUGIO AKIMASA</au><au>MANBA HIROSHI</au><au>NAKAI JUNJI</au><au>TAKAHASHI TSUTOMU</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>METHOD OF TESTING ELECTRONIC CIRCUIT CONDITION</title><date>1991-11-21</date><risdate>1991</risdate><abstract>PURPOSE:To improve a test accuracy by setting the output of an electronic circuit component to be tested to a high impedance condition by a test mode signal in the electronic circuit component connected to the input side of the electronic circuit component to be tested. CONSTITUTION:Probes 60a-63a are brought into contact with test pads 60b-63b, respectively. Then, a test mode signal S1 is inputted from a tester 64 to a tri-state buffer 53c via the probe 60a to set the output side lead 53b of an IC chip 53 to a high impedance condition. At the same time, a test drive signal S3 is inputted to the tri-state buffer 56c from the tester 64 to activate the try state buffer 56c. Thus, the effect of the IC chip 53 is removed over a range from a wiring pattern 57 to the IC chip 57.</abstract><oa>free_for_read</oa></addata></record>
fulltext fulltext_linktorsrc
identifier
ispartof
issn
language eng
recordid cdi_epo_espacenet_JPH03261882A
source esp@cenet
subjects CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS
ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
MEASURING
MEASURING ELECTRIC VARIABLES
MEASURING MAGNETIC VARIABLES
PHYSICS
PRINTED CIRCUITS
TESTING
title METHOD OF TESTING ELECTRONIC CIRCUIT CONDITION
url https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2024-12-18T00%3A35%3A24IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-epo_EVB&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=SUGIO%20AKIMASA&rft.date=1991-11-21&rft_id=info:doi/&rft_dat=%3Cepo_EVB%3EJPH03261882A%3C/epo_EVB%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true