RECEPTION CLOCK RECOVERY SYSTEM

PURPOSE:To discriminate the connection polarity and to recover the reception clock by providing a PLL circuit comparing phases of logic level signals near a frequency twice the data clock frequency and a reception clock phase decision circuit section using a shift register transferring a logic level signal while using the output of the PLL circuit as a shift clock. CONSTITUTION:A reception clock recovery circuit is provided with an amplitude limit amplifier circuit 30, a PLL circuit 32, a shift register 33, an exclusive OR circuit 34, a binary counter 35, a polarity discrimination flip-flop circuit 36, a clock switching circuit 37 and a start control circuit 38. Then the connection polarity of an amplitude phase modulation signal is discriminated by using an oscillation output of the PLL circuit 32 applying phase comparison to a logic level signal of an amplitude phase modulation signal through the use of a frequency being nearly twice the data clock frequency as a shift clock so as to process the logic level signal and the phase of the reception clock is set only once by the start control circuit 38. Thus, the reception clock corresponding to the connection polarity of the amplitude phase modulation signal is generated.