LOGIC SIMULATION MODEL PREPARING METHOD

PURPOSE:To shorten time for preparing a simulation model by preparing the new simulation model from the simulation model, which is prepared from the circuit data of a logical block including parts with the existence of a change, and the simulation model of the logical block in the other part based o...

Ausführliche Beschreibung

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Bibliographische Detailangaben
Hauptverfasser: TAKAGI TOMIE, MIZOGAMI YOSHITO, NAGURA YASUO
Format: Patent
Sprache:eng
Schlagworte:
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Beschreibung
Zusammenfassung:PURPOSE:To shorten time for preparing a simulation model by preparing the new simulation model from the simulation model, which is prepared from the circuit data of a logical block including parts with the existence of a change, and the simulation model of the logical block in the other part based on control information and connection information. CONSTITUTION:A simulation model 406 is provided so as to be divided for the unit of the logical block for a logic circuit before a change, and the simula tion model 406 before the change is composed of the connection information for the respective logical block levels and the control information showing capacity (lengths l1-l4) for each logical block level to occupy on the memory of a computer or address information (position). With the circuit data of the logical block with the existence of the change or a high-order hierarchy as the input, while limiting the preparation of the simulation model of the logical block only for the change logical block, the simulation model of the change logical block is prepared and based on the control information and the connec tion information, the simulation model is newly prepared. Thus, the time is shortened for preparing the simulation model.