JPH0324057B

A semiconductor device comprises a semiconductor chip (2l) having main power supply lines (23, 24, 26, 27) which are arranged in peripheral regions in the vicitity of edges of the semiconductor chip and which are formed with multi-level metallization. The main power supply lines are formed with arra...

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Bibliographische Detailangaben
Hauptverfasser: HIROKI TERUO, SHIRATO TAKEHIDE
Format: Patent
Sprache:eng
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Zusammenfassung:A semiconductor device comprises a semiconductor chip (2l) having main power supply lines (23, 24, 26, 27) which are arranged in peripheral regions in the vicitity of edges of the semiconductor chip and which are formed with multi-level metallization. The main power supply lines are formed with arrangements in that layers (23a, 27a; 24a, 26a) of the same potential face each other through an insulating layer in chip corner regions (2la) adjacent to corners of the semiconductor chip.