FLIP-FLOP CIRCUIT WITH RESET FUNCTION

PURPOSE:To interrupt circuit power at reset state by providing a circuit generating a reset signal for a FF and a current adjustment signal from an external reset signal and providing a delay means between the circuit and the FF. CONSTITUTION:A gate voltage of a constant current FFTJ 11 is controlled by a current adjustment signal VR1 and a current I1 flows to the circuit. When a level of the signal VR1 gets higher, the circuit current is increased. A FF1 outputs an input signal DIN synchronously with a clock signal CK. When a reset signal SR is inputted, the FF 1 outputs an H or L level signal independently of the signal DIN or the CK. While an external reset signal RS0 is not inputted, a signal generating circuit 2 generates an L level as the reset signal RS1 and an H level as the signal VR1, and a prescribed circuit current flows to the FF 1. When the signal RS0 is at an L level, the FF acts like a conventional FF and when the RS0 changes from L to H, the VR1 changes from H to L and the circuit current of the FF 1 is interrupted. On the other hand, when the signal RS0 changes from L to H, the circuit current of the FF 1 is arisen and a current flows to the circuit.