INPUT CIRCUIT

PURPOSE:To prevent a malfunction and to decrease current consumption by interposing plural FET transistors(TRs) between an input terminal and a 1st power supply to provide a difference to a driving capability of each TR. CONSTITUTION:When a bipolar TR 1 is turned off, a current from a 1st power line...

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Bibliographische Detailangaben
1. Verfasser: YAMANE HIROTAKA
Format: Patent
Sprache:eng
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Beschreibung
Zusammenfassung:PURPOSE:To prevent a malfunction and to decrease current consumption by interposing plural FET transistors(TRs) between an input terminal and a 1st power supply to provide a difference to a driving capability of each TR. CONSTITUTION:When a bipolar TR 1 is turned off, a current from a 1st power line 23 is not fed to an input terminal 25 and since a FET 2 is always turned on, the potential of the terminal 25 goes to a low level. In this case, since an output of a buffer circuit 20 goes to a high level, a FET 3 is also turned on and a potential at the terminal 25 remains in a low potential. When the TR 1 is turned on, currents I2, I3 flow from the power line 23, a potential at the terminal 25 rises attended therewith, an output of the circuit 20 goes to a low level and he FET 3 is turned off. In this case, the flowing current is only the current I2. Then by giving a difference to the driving capability of the FETs 2, 3, the current consumption is saved without slowing down a series of operation and the influence of noise is suppressed to a same degree as that of a conventional circuit.