MULTIPLICATION DEVICE

PURPOSE:To realize high-speed multiplication through less hardware quantity by executing the accumulation of a partial product by the number system of redundant binary system representation in which carry is not propagated at the time of addition, and executing plural number of times of the accumula...

Ausführliche Beschreibung

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Bibliographische Detailangaben
Hauptverfasser: MIYAZAKI HIROYUKI, KIYOHARA TOKUZO
Format: Patent
Sprache:eng
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Beschreibung
Zusammenfassung:PURPOSE:To realize high-speed multiplication through less hardware quantity by executing the accumulation of a partial product by the number system of redundant binary system representation in which carry is not propagated at the time of addition, and executing plural number of times of the accumulation of the partial product during one machine cycle. CONSTITUTION:Since a multiplier register 3 is right-shifted by one bit whenever the accumulation of the partial product is executed, a digit to which the partial product is to be added when the accumulation is executed next time appears in the least significant bit. A shifting number control part 5 instructs a partial product generating device 8 to output '0' when input from the multiplier register 3 is '0', and to output the output of a multiplicand register 7 when the input is '1'. Since a value which is always left-shifted by one bit is outputted from the partial product generating device 8 to the multiplicand register 7 regardless of the instruction of the shifting number control device 5, the value of the multiplicand register 7 is shifted by one digit whenever the accumulation is executed. Thus, an arithmetic unit 10 can execute arithmetic operation at high speed since the propagation of the carry is not caused for adding a redundant binary number.