SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE
PURPOSE:To make it possible to obtain trench isolation grooves having good interelement isolation characteristics by a method wherein intrinsic gettering layers are formed on places, where are situated sufficiently deeper than the lower parts of trench grooves, in a semiconductor substrate. CONSTITU...
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Format: | Patent |
Sprache: | eng |
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Zusammenfassung: | PURPOSE:To make it possible to obtain trench isolation grooves having good interelement isolation characteristics by a method wherein intrinsic gettering layers are formed on places, where are situated sufficiently deeper than the lower parts of trench grooves, in a semiconductor substrate. CONSTITUTION:A second conductivity type buried layer 2 is provided in a first conductivity type semiconductor substrate 1 and a second conductivity type epitaxially grown layer 3 is formed thereon. After trench grooves 4 to reach the substrate 1 are formed by etching, an impurity, such as phosphorus or the like, is ion-implanted in parts, which correspond to the bottoms of the grooves 4, in the substrate for forming intrinsic gettering layers. At that time, even after all heat treatments in the latter process are performed, the impurity is ion-implanted at a high energy so that the intrinsic gettering layers 7 are formed on places sufficiently deeper than the interfaces between the bottoms of the grooves 4 and the substrate. Then, first conductivity type buried layers 5 which are used as isolation channel cut layers are formed and moreover, an embedding material is buried in the grooves 4. Thereby, trench isolation grooves having good interelement isolation characteristics are obtained. |
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