MANUFACTURE OF SEMICONDUCTOR DEVICE

PURPOSE:To obtain a high reliability MOSFET with narrow gate length by a method wherein, when a bipolar type transistor and an MOS type transistor are formed on the same substrate, an LDD structure is used and a side wall forming process to narrow the emitter width is applied to the MOS side. CONSTITUTION:An N layer 42 and a p layer 43 are buried in a P type substrate 41; an N epitaxial layer 44 is stacked and regions 50, 46, 48 are formed; element isolation is performed. An SiO2 film 52 is selectively eliminated; poly-Si is stacked; patterns 54a, 54b are formed by using an Si3N4 mask, and SiO2 60 is formed. An inactive base is formed by implanting B; SiO2 is etched, and a pattern side wall is newly covered with SiO2 63. An active base 64 and a P offset layer 65 are formed by implanting B; an N offset layer 66 is formed by implanting E. SiO2 and poly-Si are stacked; RIE is performed, a side wall 69 is formed; an emitter aperture 62 is narrowed; thus, on the MOS side, an LDD structure is realized by the side wall 69. After that, electrodes 73-76 of doped poly Si are formed, SiO2 and BPSG 78 are stacked; by heat treatment, the source drain of LDD is formed as the combination of a P layer 82 and the P offset layer 65 and an N layer 81 and the N offset layer 66; a window and a wiring are formed, thereby completing a CMOS structure.