DATA PROCESSOR

PURPOSE:To improve processing capacity as a whole data processor by controlling a gate circuit if CPU in a processor is in an internal processing state, setting an internal bus and an external bus to be a non-condition state and outputting the use permission signal of the external bus to a peripheral equipment. CONSTITUTION:When a timing control circuit 11a detects that the processing of CPU 11 is an internal processing which does not use the external bus 20, it shifts a system between the internal bus 11e and the external bus 20 to be the non-connection state by dropping a strobe signal STB supplied to the gate circuit 13 to be low. When it receives a holding request signal HLDR from a DMA controller 23, it continues the internal processing state and returns the use permission signal of the external bus in the form of HLDA, which shows a shift to a holding state. Thus, the internal processing of the processor and data transfer by the peripheral equipment through the external bus can be executed in parallel and processing capacity as the whole data processor can be improved.