SEMICONDUCTOR INTEGRATED CIRCUIT

PURPOSE:To save a wasteful current by detecting potential at an input terminal, and controlling the current on the input terminal in terms of time. CONSTITUTION:A prescribed clock 101 is inputted from a terminal 52 to the input circuit, and the clock 101 and an input logic level 103 are inputted to...

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Bibliographische Detailangaben
1. Verfasser: YAMANE HIROTAKA
Format: Patent
Sprache:eng
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Zusammenfassung:PURPOSE:To save a wasteful current by detecting potential at an input terminal, and controlling the current on the input terminal in terms of time. CONSTITUTION:A prescribed clock 101 is inputted from a terminal 52 to the input circuit, and the clock 101 and an input logic level 103 are inputted to a NOR circuit 3, and NOR output 104 is inputted to the gate of an enhancement type P-MOS transistor 1. The on-off operation of the enhancement type P-MOS transistor 1 is controlled synchronizing with the clock 101, and the current I1 flows from a first power source to a second power source via the enhancement type P-MOS transistor 1 and a transistor 4 only at a timing when an onstate is set. Therefore, it is possible to prevent the current I1 continued to flow even at a state where the logic level at the input terminal 51 is LOW.