FRAME SYNCHRONIZING SYSTEM

PURPOSE:To eliminate the influence of a burst error by branching a reception series into 3 or above of odd number of series, inserting a delay being the multiple of integer of a frame period different from each system at every series and extracting a frame synchronizing position from the output series of majority operation. CONSTITUTION:A branching circuit(DC) 2 receives a reception series(RS) 32 to generate 3 branching series (RS0, RS1 and RS2) 3-5, delay circuits (D1, D2) 6, 7 receive the RS1 4, RS2 5 to generate delay insertion series (DS1, DS2) 8, 9. Where, the delay tau1 of the D1 6 is the multiple of integer of a frame period Tp and set longer than a burst error generation period TB in the RS 32. Moreover, the delay tau2 of the D2 7 is selected to be different from the delay tau1 of the D1 6 such as nearly twice the tau1. Then a majority operation circuit (ML) 10 receives the RS03, DS18, DS29, the signals are subjected to the majority operation to generate a majority operation output series (MS) 11 and the MS 11 is inputted to a frame synchronizing position extraction circuit (SYN) 31. Thus, the proof stress against the burst error is improved.