SEMICONDUCTOR DEVICE

PURPOSE:To enable the rapid formation of a depletion layer inside a high resistivity layer and to improve a semiconductor device more in switching speed by a method wherein at a least a hole is provided to the high resistivity layer extending from a surface side to an insulating base, and a control...

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Bibliographische Detailangaben
Hauptverfasser: IPPOSHI TAKASHI, SUGAHARA KAZUYUKI, IWAMATSU TOSHIAKI, YAMAGUCHI YASUO, INOUE YASUAKI
Format: Patent
Sprache:eng
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Beschreibung
Zusammenfassung:PURPOSE:To enable the rapid formation of a depletion layer inside a high resistivity layer and to improve a semiconductor device more in switching speed by a method wherein at a least a hole is provided to the high resistivity layer extending from a surface side to an insulating base, and a control electrode layer is formed on the high resistivity layer and inside the hole concerned. CONSTITUTION:When a zero or a positive voltage is applied to a gate layer 7 as keeping a first N-type single crystal silicon layer 3 at a zero potential and applying a positive potential to a second N-type single crystal silicon layer 4, electrons from the first N-type single crystal silicon layer 3 pass through an intrinsic layer 5, and a current flows. On the other hand, the first N-type single crystal silicon layers 3 and 4 are kept at a zero and a positive potential respectively, and a negative potential is applied to the gate layer 7 keeping the layers 3 and 4 in this state. In this state, electrons in the intrinsic layer 5 around the gate layer 7 are expelled to make the layer 5 depleted. At this point, a part of the intrinsic layer 5 is replaced with the gate layer 7, so that a negative voltage is applied to the intrinsic layer 5 in a lateral direction. By this setup, a depletion layer is rapidly formed in the intrinsic layer 5, so that a semiconductor device of this design can be improved in switching speed.