LEVEL CONVERTING CIRCUIT

PURPOSE:To make the logic level stable and to suppress the production of a DC current by providing a P-channel MOSFET to a base of an emitter follower output transistor(TR) and an N-channel MOSFET to the emitter in a differential TR circuit. CONSTITUTION:An input signal is given to a gate of P-channel MOSFETs Q1, Q3 and a gate of N-channel MOSFETs Q2, Q4 with a level difference by a voltage drop of resistors R3, R4 and a hase-emitter voltage VBE of TRs T3, T4 with respect to an output signal of a differential TR circuit. Thus, even when an ECL level to be level-converted is at a midpoint potential, the conductance of the FETs Q1, Q3 and the FETs Q2, Q4 is comparatively decreased. Then a DC current flowing through the FETs Q1, Q2 and Q3, Q4 is limited. Since the ratio of the conductance of the FET Q1 turned on at a low level is adopted larger, the stability of the operation is attained.