MEMORY ACCESS CIRCUIT

PURPOSE:To realize the high efficiency of an access by executing the writing and reading of data in a memory in response to the writing and reading signal received by a memory control means. CONSTITUTION:In a reading mode, selecting switches 12 and 18 are switched to an R side, an input/output contr...

Ausführliche Beschreibung

Gespeichert in:
Bibliographische Detailangaben
1. Verfasser: TAKANO TOSHINORI
Format: Patent
Sprache:eng
Schlagworte:
Online-Zugang:Volltext bestellen
Tags: Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
Beschreibung
Zusammenfassung:PURPOSE:To realize the high efficiency of an access by executing the writing and reading of data in a memory in response to the writing and reading signal received by a memory control means. CONSTITUTION:In a reading mode, selecting switches 12 and 18 are switched to an R side, an input/output control part 20 becomes a reading mode by a reading enable IB signal E1, a precharging circuit 6 and a sense amplifier 8 are operated by an IB signal E3, and data read from a memory cell 2 by the address designation from address input terminals RAL to RAn are outputted from output terminals RD1 to RDm through the amplifier 8, the control part 20 and switches 241 to 24m. In a writing mode, switches 12 and 18 are switched to a W side, the control part 20 becomes the writing mode by a writing IB signal E2, and the circuit 6 and the amplifier 8 are operated by the signal E3. By the address designation from input terminals WA1 to WAn, the data inputted to input terminals WD1 to WDn are written through a switch 18 and the control part 20 to the memory cell 2 by the signal E2.