MEMORY CONTROL SYSTEM

PURPOSE:To expand the bit width of a data area corresponding to each address by applying the same address signal on plural read-only memory chips with fixed bit width by providing them in the same package, and controlling data output sequence from the read-only memory chips by a chip select signal....

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1. Verfasser: KAGEYAMA YOSHIAKI
Format: Patent
Sprache:eng
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Zusammenfassung:PURPOSE:To expand the bit width of a data area corresponding to each address by applying the same address signal on plural read-only memory chips with fixed bit width by providing them in the same package, and controlling data output sequence from the read-only memory chips by a chip select signal. CONSTITUTION:A single read-only memory in which the plural read-only memory chips 3 and 4 are provided in the same package 5 is formed, and the output of data with expanded bit width is performed by applying address signals ADR0- ADR2n-1 and the chip select signal CS. And a line is connected to the address input terminal of the package 5 so that the same address signals ADR0-ADR2n-1 can be applied on the address input contacts of the memory chips 3 and 4, and the output contacts of the plural memory chips 3 and 4 is connected to a data select circuit 6. Thereby, it is possible to perform the output of the data with the expanded bit width by performing the same address designation as the use of an ordinary memory in the single read-only memory formed by incorporating the plural memory chips 3 and 4 with the fixed bit width.