SPLIT PHASE DECODING CIRCUIT

PURPOSE:To obtain NRZ decoding output in which a split phase code is decoded with correct polarity by detecting noncoincidence between the output of a butter and that of a delay means, and switching the polarity of a clock outputted from a selector. CONSTITUTION:A noncoincidence detection circuit 8 detects the noncoincidence between output signals 7' and 9', and generates an output signal 10', and an integration circuit 9 integrates the output signal 10'. A comparator 10 generates output 12', which goes to '1' when an output signal 11, is less than a constant threshold value level Vth2 and goes to '0' when it exceeds a threshold value level Vth2. When the output signal 12', of the comparator 10 is '1', the clock 4', or 5', is selected at the selector 3 so that the clock 6', can be started up at the latter part of split phase data. In such a way, it is possible to obtain the output signal consisting of NRZ data in which the split phase data 2'. is demodulated correctly at output 7'.