SEMICONDUCTOR INTEGRATED CIRCUIT

PURPOSE:To increase signal wiring patterns and to implement a compact configuration by supplying power to an outermost logic block group in a semiconductor chip through power source wirings which are provided individually from chip power feeding terminals directly without providing main power source...

Ausführliche Beschreibung

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Bibliographische Detailangaben
Hauptverfasser: HIRAI KAZUHIRO, KATADA TOSHIYUKI
Format: Patent
Sprache:eng
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Beschreibung
Zusammenfassung:PURPOSE:To increase signal wiring patterns and to implement a compact configuration by supplying power to an outermost logic block group in a semiconductor chip through power source wirings which are provided individually from chip power feeding terminals directly without providing main power source lines. CONSTITUTION:A semiconductor chip 1 has a plurality of logic blocks 2 which are arranged in a matrix pattern. A plurality of power feeding terminals 3 for feeding power to the logic blocks 2 are provided around the logic blocks 2. The block power feeding terminals 3 are connected to chip shaped power feeding terminals 4. At least one main power source line 8 is regularly provided for every power potential in a wiring region 5 between the blocks. The main power source line 8 is not provided at the outside of the peripheral logic blocks 2 in the semiconductor chip 1. The block power feeding terminals 3 are directly connected to the chip power feeding terminals 4. Since the number of the main power source lines 8 as the first wirings can be decreased in this way, the signal wiring patterns can be increased by that amount, and the circuit can be made compact.