INSTRUCTION PRECEDENCE CONTROL SYSTEM

PURPOSE:To reduce number of cycle of a jump (J) instruction and to improve throughput by not discarding but using the next instruction of a jump-and-link (JL) instruction. CONSTITUTION:When the instruction at an (m) address is set at the JL instruction, the next instruction at an m+1 address is shif...

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Bibliographische Detailangaben
Hauptverfasser: NAGABORI KAZUO, TANIHIRA HISAMITSU
Format: Patent
Sprache:eng
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Zusammenfassung:PURPOSE:To reduce number of cycle of a jump (J) instruction and to improve throughput by not discarding but using the next instruction of a jump-and-link (JL) instruction. CONSTITUTION:When the instruction at an (m) address is set at the JL instruction, the next instruction at an m+1 address is shifted from a first instruction register 11 to a second precedence instruction register 12. Further, when the execution of the instruction in a jump destination is completed, a return detecting part 14 detects the return from a sub-routine, and switches a selector 13 to the second precedence instruction register 12 side. Consequently, the instruction from the m+1 address after the return is applied through the selector 13 to an instruction register 15, and the next instruction can be promptly executed. Thus, the throughput can be improved.