JPH0240219B

An integrated (silicon based) packaging/wiring concept provides for the VLSI chips (4) to be placed within openings of somewhat larger size in a semiconductor interconnection wafer (IW, 2) supported by a carrier (1). The interconnection wafer (2) bears multilevel (ML) wiring planes and has incorporated circuit components integrated in a less demanding technology as compared to the VLSI chips (4). Silicon contact chips (5) with conductive surface layers (22, 23) placed over the chip/IW plane provide for the required interconnections by means of needle- like structures (24) inserted in corresponding via holes which needles are better suited as to shear strain encountered with conventional C-4 (Controlled Collapse Chip Connection) joints; consequently a much higher number of chip pads can be allowed. Power supply is effected via rather large-dimensioned conductive planes, e.g. in the form of Cu rails (20), running within the carrier (1) and surfacing stud-like (at 21) in the peripheral region of said openings in the interconnection wafer (2) for further distribution via the contact chip (5). The wiring system can be supplemented, if required, with an additional wiring wafer (6).