SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE

PURPOSE:To enhance the arbitrariness of logic cell arrangement without decreasing the arbitrariness of wiring information layout of a logic cell by dividing a source wiring in the arrays of transistors into a logical configuration source wiring, a main connection source wiring and a subordinate connection source wiring. CONSTITUTION:P-ch transistor 102 and N-ch transistor 103 comprise gate electrodes 104 which are electrically isolated. Logical configuration source wirings 105 and 106 set in a logic cell region 10 composed by adding the wiring information, main connection source wirings 110 and 111 which are set in the region where a logic cell is not composed and are vertical to gate electrodes 104 of transistors, and subordinate connection wirings 107 and 108 which are set in the region where a logic cell is not composed and are horizontal to the gate electrodes of transistors exist in the same transistor array region and are electrically connected to supply an electric source to the basic cell 102. Thus, the arbitrariness in arrangement of the logic cell 109 and that of wirings in the cell for composing the logic cell 109 can be improved.