CODING MODE INFORMATION TRANSMISSION SYSTEM

PURPOSE:To avoid the increase in mode information bit number and the reduction in mode switching speed and to provide a 1-bit error correction function by deciding the mode type depending on the detection content of the type of a frame pattern and generating plural kinds of the modes. CONSTITUTION:A...

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Bibliographische Detailangaben
Hauptverfasser: TANAKA TAKESHI, KAJIWARA MASANORI, MASE HIDEKI
Format: Patent
Sprache:eng
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Zusammenfassung:PURPOSE:To avoid the increase in mode information bit number and the reduction in mode switching speed and to provide a 1-bit error correction function by deciding the mode type depending on the detection content of the type of a frame pattern and generating plural kinds of the modes. CONSTITUTION:A pattern of the mode 1 is given to a shift register 21 in a frame pattern detection section 20c at the reception side, outputs QD, QB, QC, QA all go to '1' and the level is given to an AND circuit 22. On the other hand, when a pattern of the mode 2 is given, outputs QD, QB, QC, QA all go to '1' and the level is given to an AND circuit 23. A frame synchronizing circuit 4 fetches OR outputs from the AND circuits 22, 23 from an OR circuit 31 and sends a pulse 1. A JK-F.F circuit 34 is inoperative except the frame pattern inserting position. When the pattern of the mode 1 is detected at the frame pattern inserting position, its output goes to '0', while the pattern of the mode 2 is detected at the frame pattern inserting position, its output goes to '1'.