INSTRUCTION EXCUTING METHOD AND SYSTEM

PURPOSE: To shorten the execution time of an instruction stream by using the operation mechanism of a main processor to simultaneously execute another instruction in the shared stream before completion of execution of a preceding instruction in a coprocessor. CONSTITUTION: A main processor 110 execu...

Ausführliche Beschreibung

Gespeichert in:

Bibliographische Detailangaben
Hauptverfasser:	TOOMASU JIYOSEFU BIIKOMU, SUKOTSUTO AREN HIRUKAA, DANIERU GAI YANGU, MAAKU ROBAATO FUANKU, JIEFURII DAGURASU BURAUN
Format:	Patent
Sprache:	eng
Schlagworte:	CALCULATING COMPUTING COUNTING ELECTRIC DIGITAL DATA PROCESSING PHYSICS
Online-Zugang:	Volltext bestellen
Tags:	Tag hinzufügen Keine Tags, Fügen Sie den ersten Tag hinzu!

container_end_page
container_issue
container_start_page
container_title
container_volume
creator	TOOMASU JIYOSEFU BIIKOMU SUKOTSUTO AREN HIRUKAA DANIERU GAI YANGU MAAKU ROBAATO FUANKU JIEFURII DAGURASU BURAUN
description	PURPOSE: To shorten the execution time of an instruction stream by using the operation mechanism of a main processor to simultaneously execute another instruction in the shared stream before completion of execution of a preceding instruction in a coprocessor. CONSTITUTION: A main processor 110 executes non-floating-point instructions, and a coprocessor 120 executes only floating-point instructions. Data routes and operations of processors are controlled by control words held in a control storage 130, and the address of the next control word to be executed is designated. Data is transferred between two processors 110 and 120 by a normal processor bus 111, and execution of control words in the main processor 110 is inhibited by a holding line 112. Thus different instructions are executed in parallel while keeping the successive operation or the instruction stream and accurate exceptional interrupts.
format	Patent
fullrecord	<record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_JPH02294830A</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>JPH02294830A</sourcerecordid><originalsourceid>FETCH-epo_espacenet_JPH02294830A3</originalsourceid><addsrcrecordid>eNrjZFDz9AsOCQp1DvH091NwjXAODfH0c1fwdQ3x8HdRcPRzUQiODA5x9eVhYE1LzClO5YXS3AyKbq4hzh66qQX58anFBYnJqXmpJfFeAR4GRkaWJhbGBo7GxKgBAOoBJAk</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>INSTRUCTION EXCUTING METHOD AND SYSTEM</title><source>esp@cenet</source><creator>TOOMASU JIYOSEFU BIIKOMU ; SUKOTSUTO AREN HIRUKAA ; DANIERU GAI YANGU ; MAAKU ROBAATO FUANKU ; JIEFURII DAGURASU BURAUN</creator><creatorcontrib>TOOMASU JIYOSEFU BIIKOMU ; SUKOTSUTO AREN HIRUKAA ; DANIERU GAI YANGU ; MAAKU ROBAATO FUANKU ; JIEFURII DAGURASU BURAUN</creatorcontrib><description>PURPOSE: To shorten the execution time of an instruction stream by using the operation mechanism of a main processor to simultaneously execute another instruction in the shared stream before completion of execution of a preceding instruction in a coprocessor. CONSTITUTION: A main processor 110 executes non-floating-point instructions, and a coprocessor 120 executes only floating-point instructions. Data routes and operations of processors are controlled by control words held in a control storage 130, and the address of the next control word to be executed is designated. Data is transferred between two processors 110 and 120 by a normal processor bus 111, and execution of control words in the main processor 110 is inhibited by a holding line 112. Thus different instructions are executed in parallel while keeping the successive operation or the instruction stream and accurate exceptional interrupts.</description><language>eng</language><subject>CALCULATING ; COMPUTING ; COUNTING ; ELECTRIC DIGITAL DATA PROCESSING ; PHYSICS</subject><creationdate>1990</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=19901205&DB=EPODOC&CC=JP&NR=H02294830A$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,776,881,25543,76293</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=19901205&DB=EPODOC&CC=JP&NR=H02294830A$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>TOOMASU JIYOSEFU BIIKOMU</creatorcontrib><creatorcontrib>SUKOTSUTO AREN HIRUKAA</creatorcontrib><creatorcontrib>DANIERU GAI YANGU</creatorcontrib><creatorcontrib>MAAKU ROBAATO FUANKU</creatorcontrib><creatorcontrib>JIEFURII DAGURASU BURAUN</creatorcontrib><title>INSTRUCTION EXCUTING METHOD AND SYSTEM</title><description>PURPOSE: To shorten the execution time of an instruction stream by using the operation mechanism of a main processor to simultaneously execute another instruction in the shared stream before completion of execution of a preceding instruction in a coprocessor. CONSTITUTION: A main processor 110 executes non-floating-point instructions, and a coprocessor 120 executes only floating-point instructions. Data routes and operations of processors are controlled by control words held in a control storage 130, and the address of the next control word to be executed is designated. Data is transferred between two processors 110 and 120 by a normal processor bus 111, and execution of control words in the main processor 110 is inhibited by a holding line 112. Thus different instructions are executed in parallel while keeping the successive operation or the instruction stream and accurate exceptional interrupts.</description><subject>CALCULATING</subject><subject>COMPUTING</subject><subject>COUNTING</subject><subject>ELECTRIC DIGITAL DATA PROCESSING</subject><subject>PHYSICS</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>1990</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZFDz9AsOCQp1DvH091NwjXAODfH0c1fwdQ3x8HdRcPRzUQiODA5x9eVhYE1LzClO5YXS3AyKbq4hzh66qQX58anFBYnJqXmpJfFeAR4GRkaWJhbGBo7GxKgBAOoBJAk</recordid><startdate>19901205</startdate><enddate>19901205</enddate><creator>TOOMASU JIYOSEFU BIIKOMU</creator><creator>SUKOTSUTO AREN HIRUKAA</creator><creator>DANIERU GAI YANGU</creator><creator>MAAKU ROBAATO FUANKU</creator><creator>JIEFURII DAGURASU BURAUN</creator><scope>EVB</scope></search><sort><creationdate>19901205</creationdate><title>INSTRUCTION EXCUTING METHOD AND SYSTEM</title><author>TOOMASU JIYOSEFU BIIKOMU ; SUKOTSUTO AREN HIRUKAA ; DANIERU GAI YANGU ; MAAKU ROBAATO FUANKU ; JIEFURII DAGURASU BURAUN</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_JPH02294830A3</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>1990</creationdate><topic>CALCULATING</topic><topic>COMPUTING</topic><topic>COUNTING</topic><topic>ELECTRIC DIGITAL DATA PROCESSING</topic><topic>PHYSICS</topic><toplevel>online_resources</toplevel><creatorcontrib>TOOMASU JIYOSEFU BIIKOMU</creatorcontrib><creatorcontrib>SUKOTSUTO AREN HIRUKAA</creatorcontrib><creatorcontrib>DANIERU GAI YANGU</creatorcontrib><creatorcontrib>MAAKU ROBAATO FUANKU</creatorcontrib><creatorcontrib>JIEFURII DAGURASU BURAUN</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>TOOMASU JIYOSEFU BIIKOMU</au><au>SUKOTSUTO AREN HIRUKAA</au><au>DANIERU GAI YANGU</au><au>MAAKU ROBAATO FUANKU</au><au>JIEFURII DAGURASU BURAUN</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>INSTRUCTION EXCUTING METHOD AND SYSTEM</title><date>1990-12-05</date><risdate>1990</risdate><abstract>PURPOSE: To shorten the execution time of an instruction stream by using the operation mechanism of a main processor to simultaneously execute another instruction in the shared stream before completion of execution of a preceding instruction in a coprocessor. CONSTITUTION: A main processor 110 executes non-floating-point instructions, and a coprocessor 120 executes only floating-point instructions. Data routes and operations of processors are controlled by control words held in a control storage 130, and the address of the next control word to be executed is designated. Data is transferred between two processors 110 and 120 by a normal processor bus 111, and execution of control words in the main processor 110 is inhibited by a holding line 112. Thus different instructions are executed in parallel while keeping the successive operation or the instruction stream and accurate exceptional interrupts.</abstract><oa>free_for_read</oa></addata></record>
fulltext	fulltext_linktorsrc
identifier
ispartof
issn
language	eng
recordid	cdi_epo_espacenet_JPH02294830A
source	esp@cenet
subjects	CALCULATING COMPUTING COUNTING ELECTRIC DIGITAL DATA PROCESSING PHYSICS
title	INSTRUCTION EXCUTING METHOD AND SYSTEM
url	https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-01-26T09%3A27%3A28IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-epo_EVB&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=TOOMASU%20JIYOSEFU%20BIIKOMU&rft.date=1990-12-05&rft_id=info:doi/&rft_dat=%3Cepo_EVB%3EJPH02294830A%3C/epo_EVB%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true