CORRECT CELL SELECTING DEVICE FOR LOGIC CIRCUIT
PURPOSE:To select a correct cell in a short time by using a ratio in which a delay time of a logical gate to be taken notice of is occupied in the passing time of a signal and two degrees of freedom as evaluation functions, and deciding whether a cell used by the logical gate to be taken notice of i...
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Format: | Patent |
Sprache: | eng |
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Zusammenfassung: | PURPOSE:To select a correct cell in a short time by using a ratio in which a delay time of a logical gate to be taken notice of is occupied in the passing time of a signal and two degrees of freedom as evaluation functions, and deciding whether a cell used by the logical gate to be taken notice of is changed to a cell whose driving capacity is different or not and changing it. CONSTITUTION:This device is provided with a circuit diagram file 1, a data base 2 for degree of freedom 1, a data base 3 for degree of freedom 2, a delay time calculating device 4, an evaluation value calculating device 5, and a cell replacing device 6. In this state, by an evaluation value calculated from a value obtained from the degree of freedom of a change of a cell used by each logical gate and the degree of freedom of a cell used by a logical date being in its pre-stage, and a ratio to an average value of the delay time of all the logical gates, of the delay time of each logical gage known already as a result of delay calculation, the logical gate whose correction effect is considered to be high is recognized. In such a way, as for a delay time calculation required for changing the driving capacity of plural logical gates of one logic circuit, it will suffice that it is executed once. |
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