FORMING METHOD FOR EMITTER-COUPLED LOGIC CIRCUIT

FORMING METHOD FOR EMITTER-COUPLED LOGIC CIRCUIT

PURPOSE:To improve integration of a circuit by disposing elements so that NPN bipolar transistors of a differential logic unit are reversely operated, and forming all the transistors in the same well region. CONSTITUTION:NPN bipolar transistors 3, 4, 5 of a differential logic unit are used at nodes...

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Bibliographische Detailangaben
1. Verfasser: NAGAMATSU TORU
Format: Patent
Sprache:eng
Schlagworte:
BASIC ELECTRIC ELEMENTS
BASIC ELECTRONIC CIRCUITRY
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
PULSE TECHNIQUE
SEMICONDUCTOR DEVICES
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Beschreibung
Zusammenfassung:PURPOSE:To improve integration of a circuit by disposing elements so that NPN bipolar transistors of a differential logic unit are reversely operated, and forming all the transistors in the same well region. CONSTITUTION:NPN bipolar transistors 3, 4, 5 of a differential logic unit are used at nodes normally used as collectors as emitters, and at nodes normally used as emitters as collectors. They are disposed to be reversely operated. With such a structure, the transistors 3, 4, 5 can be formed in the same well region in the logic unit to improve integration of the circuit.