INPUT BUFFER CIRCUIT FOR SEMICONDUCTOR INTEGRATED CIRCUIT

PURPOSE:To eliminate the need for the conversion of an input level with one kind of an input buffer circuit by providing the transmission gate of an N- channel MOS transistor(TR) on the pre-stage of an input buffer circuit for semiconductor integrated circuit. CONSTITUTION:Let the source level of an...

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Hauptverfasser: HOKIMOTO TAKEHIRO, OKAYASU HIDEKI
Format: Patent
Sprache:eng
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Zusammenfassung:PURPOSE:To eliminate the need for the conversion of an input level with one kind of an input buffer circuit by providing the transmission gate of an N- channel MOS transistor(TR) on the pre-stage of an input buffer circuit for semiconductor integrated circuit. CONSTITUTION:Let the source level of an N-channel MOS TR(NMOS TR) 2 be Vin, a gate level be Vg, a drain level be Vo, and a threshold voltage be Vth, then the relation of Vo=Vin exists in the operation at the linear region of the TR 2, and the relation of Vo=Vg-Vth exists in the operation at the saturation region of the TR 2. When the signal of a CMOS level is inputted from an input terminal 1, a signal with a level nearly equal to a TTL level signal is outputted from the drain electrode of the TR 2. When the signal of a TTL level is inputted from the input terminal 1, since the TR 2 is operated at a linear region, a signal whose level is nearly equal to the input level is outputted from the drain. Thus, even when an input signal with a different level is inputted from an external input terminal, the signal with a nearly equal level is outputted from the drain.