SEMICONDUCTOR STORAGE DEVICE

PURPOSE:To reduce the area of a chip to be occupied by a circuit element for the precharge of a complementary bit line by providing a bit select switch, which executes turning-on operation in correspondence to the non-selection period of a memory cell, and an equalize switch. CONSTITUTION:DRAM (dynamic random access memory) is equipped with plural n-channel type equalizer MOSFETs Q9 to selectively short-circuit complementary common data lines CD and -CD. A timing control circuit 12 is provided to control all bit line select switches 9 and the FETs Q9 to a turn-on state during the non-selection period of a memory cell 11. When these all the switches 9 and FETs Q9 are controlled to the turn-on state during the non- selection period of the memory cell 11, a pair of complementary bit lines BLi and -BLi, for which a level is forcibly set according to a power supply voltage Vdd and a ground voltage Vss, are conducted and thus, all the lines BLi and -BLi are balanced to a voltage almost half of the voltage Vdd. Thus, an exclusive precharge circuit is not required for each complementary bit line.