SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE

PURPOSE:To facilitate layout of substrate potential generating circuits by a method wherein a plurality of the substrate potential generating circuits are separately arranged on a semiconductor chip to supply the substrate potential. CONSTITUTION:For instance, four substrate potential generating cir...

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Bibliographische Detailangaben
Hauptverfasser: MURANAKA MASAYA, MATSUURA NOBUMI, KIZAKI TAKESHI
Format: Patent
Sprache:eng
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Beschreibung
Zusammenfassung:PURPOSE:To facilitate layout of substrate potential generating circuits by a method wherein a plurality of the substrate potential generating circuits are separately arranged on a semiconductor chip to supply the substrate potential. CONSTITUTION:For instance, four substrate potential generating circuits VBG1-VBG4 are arranged separately on the four corners of a semiconductor chip 1. In this case, parameters of elements of which the four respective substrate potential generating circuits VBG1-VBG2 are composed are so determined as to satisfy the total potential supply capacity by the four circuits. With this constitution, the occupied areas of the four respective substrate potential generating circuits, can be reduced, their layout can be designed easily and, further, the vacant spaces of the chip can be so arranged to be utilized efficiently, so that the increase of the chip size be suppressed.