FLOATING POINT PROCESSOR

PURPOSE: To provide a high-speed pipeline floating point processor by providing a means for supplying first and second arithmetic process means for requesting the execution of the clock cycle of first and second numbers. CONSTITUTION: This processor is provided with a floating point control(FPC) chip 60, two floating point registers (FRF) chips 52 and 58, a pipeline and multiplier (Mul) chip 56 and an arithmetic and logic unit(Alu) chip 54 and a memory standard, an Alu instruction and a Mul instruction are sent for respective cycles. The processor starts the Mul instruction earlier than the Alu instruction for a half clock cycle. A register file is turned to a double cycle so as to read an Mul instruction operand in the first half of the read cycle of the reqister file and to read an Alu operand in the next half. The operand is sent to the Mul chip 56 or the Alu chip 54 by multiplexing the 64 bits of the respective double accuracy operands of data in the operand bus of 32 bits. Thus, a high- speed operation is made possible.